83140-580-02 b ISP1040C 1 features n pci local bus speci?cation revision 2.1 compliant n compliance with ansi scsi standard x3.131-1994 n compliance with ansi x3t10/855d scsi-3 parallel interface (spi) standard n compliance with ansi x3t10/1071d fast-20 standard n compliance with pci bus power management interface speci?cation revision 1.0 (pc97) n onboard risc processor to execute operations at the i/o control block level from the host memory n supports fast, wide, and ultra (fast-20) scsi data transfer rates n scsi initiator and target modes of operation n 32-bit, intelligent bus master, dma pci bus interface n supports pci dual-address cycle (64-bit addressing) n scsi operations executed from start to ?nish without host intervention n simultaneous, multiple logical threads n jtag boundary scan support product description the ISP1040C is a single-chip, highly integrated, bus master, scsi i/o processor for use in scsi initiator-type applications. the device interfaces the pci bus to a wide, ultra scsi bus and contains an onboard risc processor. the ISP1040C is a fully autonomous device, capable of managing multiple i/o operations and associated data transfers from initiation to completion without host cpu intervention. the ISP1040C provides power management feature support in accordance with the pci bus power management speci?cation while retaining full pin compatibility with the qlogic isp1040b. the ISP1040C block diagram is illustrated in ?gure 1. i/o bus figure 1. ISP1040C block diagram dma bus sxp scsi engine pci interface host memory host software driver request queue response queue 32-bit pci bus iocbs fifo wcs sequencers control data fifo 64 byte command fifo dma control mailbox registers risc register file alu boot code memory interface 8/16-bit data 16 address 16 ISP1040C command buffer message buffer sxp code registers parallel scsi bus ctrl/config registers external code/data memory 128 byte flash bios nvram qlogic corporation ISP1040C intelligent scsi processor data sheet www..net
2 ISP1040C 83140-580-02 b qlogic corporation isp initiator and target firmware the ISP1040C ?rmware implements a cooperative, multitasking host adapter that provides the host system with complete scsi command and data transport capabilities, thus freeing the host system from the demands of the scsi bus protocol. the ISP1040C ?rmware provides two interfaces to the host system: the command interface and the scsi transport interface. the single-threaded command interface facilitates debugging, con?guration, and error recovery. the multithreaded scsi transport interface maximizes use of the scsi and host buses. the ISP1040C switches dynamically between initiator and target modes. software drivers bios ?rmware is available for the ISP1040C. software drivers are available for the following operating systems: n aix n i 2 o n dos/windows n novell netware n os/2 n sco unix n unixware n windows 95 n windows nt i/o subsystem organization to maximize i/o throughput and improve host and scsi bus utilization, the ISP1040C incorporates a high-speed, proprietary risc processor; an intelligent scsi bus controller (scsi executive processor [sxp]); and a host bus, dual-channel dma controller. the scsi bus controller and the host bus dma controller operate independently and concurrently under control of the onboard risc processor for maximum system performance. the ISP1040C risc interface requires external program data memory. the complete i/o subsystem solution using the ISP1040C and associated supporting memory devices is shown in ?gure 2. interfaces the ISP1040C supports the following interfaces: n pci bus n risc processor n scsi executive processor pins that support these interfaces and other chip operations are shown in ?gure 3. ISP1040C scsi 16 scsi targets target target pci i/f scsi i/f risc code/data memory pci bus pci host memory iocb data 32 figure 2. i/o subsystem design using the ISP1040C
83140-580-02 b ISP1040C 3 qlogic corporation pci bus interface the ISP1040C pci bus interface supports the following: n 32-bit, intelligent bus master, burst dma host interface for fetching i/o control blocks and data transfers n 16-bit slave mode for communication with host n two channel dma controller n 128-byte data dma fifo and 64-byte command dma fifo with threshold control n pipelined dma registers for ef?cient scatter/gather operations n support for subsystem id n supports pci dual-address cycle (64-bit addressing) n support for pci cache commands n 3.3 v and 5.0 v tolerant pci i/o buffers n support for ?ash bios prom the ISP1040C is designed to interface directly to the pci local bus and operate as a 32-bit dma master. this function is accomplished through the pci bus interface unit (pbiu) containing an onboard dma controller. the pbiu generates and samples pci bus control signals, generates host memory addresses, and facilitates data transfers between host memory and the onboard dma fifo. the pbiu also allows the host to access the ISP1040C internal registers and communicate with the onboard risc processor through the pci bus target mode operation. figure 3. ISP1040C functional signal grouping extboot risc interface vdd vss power and ground misc control bsy cd diffm scsi interface ISP1040C riscstb/jtag esc1-0 raddr15-0 if/vdet a ck a tn io msg req rst sd15-0 sdp1-0 sel trig/60mhz tstout/tdo frame st op trd y devsel perr idsel serr ird y reset clk riscoe we rdata15-0 testmode0/tdi reset cbe3-0 pa r int a nvdati nvcs nvdato/subid nvclk/3v nvram control pdata7-0 pod bsyled gpio3-0 rdpar diffs earb esd eig etg ebsy esel erst scsi differential interface pci interface ad31-0 bclk bgnt breq flash bios prom fr oe fr we testmode1/tms testmode2/tck
4 ISP1040C 83140-580-02 b qlogic corporation the ISP1040C onboard dma controller consists of two independent dma channels that initiate transactions on the pci bus and transfer data between the memory and dma fifo. the two dma channels are the command dma channel and the data dma channel. the command dma channel is used mainly by the risc processor for small transfers such as fetching commands from and writing status information to the host memory over the pci bus. the data dma channel transfers data between the scsi bus and the pci bus. the pbiu internally arbitrates between the data dma channel and the command dma channel and alternately services them. each dma channel has a set of dma registers that are programmed for transfers by the risc processor. risc processor interface the ISP1040C risc processor interface supports the following: n programmable cycle time for external memory access n internal 16-bit wide data paths n execution of multiple i/o control blocks from the host memory n management of onboard host bus dma controller and scsi bus controller n reduced host intervention and interrupt overhead n capacity to generate one interrupt per i/o operation the onboard risc processor enables the ISP1040C to handle complete i/o transactions with no intervention from the host. the ISP1040C risc processor controls the chip interfaces; executes simultaneous, multiple input/output control blocks (iocbs); and maintains the required thread information for each transfer. scsi executive processor interface the ISP1040C sxp interface supports the following: n 8- or 16-bit data transfers n ultra scsi (fast-20) synchronous data transfer rates up to 40 mbytes/sec n asynchronous scsi data transfer rates up to 12 mbytes/sec n programmable scsi processor r specialized instruction set with 16-bit microword r 384-bit by 16-bit internal ram control store n 32-bit, con?gurable scsi transfer counter n command, status, message in, and message out buffers n device information storage area n on-chip, single-ended scsi transceivers (48-ma drivers) n programmable active negation the sxp provides an autonomous, intelligent scsi interface capable of handling complete scsi operations. the sxp interrupts the risc processor only to handle higher level functions such as threaded operations or error handling. packaging the ISP1040C is available in a 208-pin plastic quad ?at pack (pqfp). aix is a trademark of ibm corporation. dos, os/2, windows nt, and windows 95 are trademarks or registered trademarks of microsoft corp. novell and netware are registered trademarks of novell, inc. sco unix is a registered trademark of santa cruz operations. unix is a trademark of at&t bell laboratories. all other brand and product names are trademarks or registered trademarks of their respective holders. ?july 29, 1997 qlogic corporation, 3545 harbor blvd., costa mesa, ca 92626, (800) on-chip-1 or (714) 438-2200 speci?cations are subject to change without notice. qlogic is a trademark of qlogic corporation.
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